FIG. 1 is an illustration of a resistive memory cell 100 in relationship to a bit line 121, a word line 122, and a cell plate 110. The resistive memory cell 100 includes an access transistor 101 having one source/drain coupled to the bit line 121, a gate coupled to the word line 122, and another source/drain coupled to a bi-stable resistive material element 102. The bi-stable resistive material element 102 is also coupled a cell plate 110, which is typically shared among a plurality of resistive memory cells 100. The cell plate 110 is also coupled to a source of cell plate voltage designated as CPIN.
The bi-stable resistive material 102 can be any type of material that can be set to at least two different resistive states. The memory cell 100 may be classified based on the type of bi-stable resistive material 102. For example, in programmable conductor random access memory (PCRAM) cell the bi-stable resistive material 102 is typically a type of chalcogenide glass, while MRAM cells, phase-change cells, polymer memory cells, and other types of resistive memory cells employ other corresponding types of bi-stable resistive material 102.
By way of example, the illustrated resistive memory cell 100 is a PCRAM cell, in which the bi-stable resistive material element 102 may be respectively set to a first resistive state (e.g., approximately 10K ohm) or a second resistive state (e.g., approximately 10M ohm), via a first programming voltage (e.g. approximately 0.25 volt) and a second programming voltage (e.g., approximately −0.25 volt). The resistive memory cell 100 may be read by pre-charging the bit line 121 to a predetermined voltage while the access transistor 101 is non-conducting, and then causing the access transistor 101 to become conducting, thereby discharging the bit line 121 through the resistive memory cell 100 to the cell plate 110 for a predetermined time. If the voltage across the bi-stable resistive material 102 is of a magnitude less than the magnitude of the programming voltages, the read process will not alter the state of the bi-stable resistive material 102. The discharge rate is based on the state of the bi-stable resistive material 102.
A combination of cell plate voltage, bit line pre-charge voltage, and bi-stable resistive material 102 resistance may be chosen such that, when discharged, bit line 121 can be sensed using sensing circuits. Typically each sensing circuit is also coupled to a reference bit line, which is charged to a predetermined voltage. The predetermined voltage is set to an intermediate value between the two possible voltages of the bit line 121 being associated with the memory cell being read. The operation of the sensing circuit pulls the bit line having the higher voltage to an even higher voltage and pulls the bit line having the lower voltage down to a lower voltage (e.g., ground). Thus, after the operation of the sensing circuit, a comparator coupled to both bit lines can be used to output a digital signal corresponding to the state of the memory cell being read.
FIGS. 2A and 2B illustrate examples of portions of two resistive memory devices 200. Each memory device 200 includes a plurality of resistive memory cells 100, organized into an array by a plurality of word lines 122a-122f and a plurality of bit lines 121a-121d. Each word line (generally referred to by numeral 122) and each bit line (generally referred to by numeral 121) are identical. The alphanumeric suffixes at the end of each word line 122 and bit line 121 are for distinguishing between individual word lines 122 and bit lines 121 in FIGS. 2A and 2B.
Due to space limitations, only a limited number of word lines 122, bit lines 121, and memory cells 100 are illustrated. However, it should be appreciated that actual memory devices typically include many more word lines 122, bit lines 121, and cells 100. FIGS. 2A and 2B also illustrate a plurality of sensing circuits 300, which are used for reading information stored in the memory cells 100.
FIG. 2A is an illustration of an open architecture, where each sensing circuit 300 is associated with two bit lines (e.g., bit lines 121a and 121b) each associated with a different memory array 210. In contrast, FIG. 2B is an illustration of a folded architecture, where each sensing circuit 300 is still associated with two bit lines (e.g., 121a, 121b). However, in FIG. 2B these two bit lines are associated with alternating (i.e., odd/even) memory cells 100 of a same memory array 210.
FIG. 3 is a more detailed illustration of a sensing circuit 300. The sensing circuit 300 includes an equalization circuit 310, a reference setting circuit 320, a switching circuit 330, and a sense amplifier 340. A multi-tap power supply 360 provides power at Veq, DVC2, Vref, and Vcc voltage levels to the sensing circuit 300. A control circuit 350 provides control signals EQ, REFE, REFO, and SA_ISO to the sensing circuit 300. The use of these voltages and control signals are described in greater detail below.
The equalization circuit 310 includes two input nodes A1 and A2, each coupled to a respective bit line 121. One of the two bit lines 121 is a bit line connected to a memory cell 100 which will be read. The other bit line is another bit line 121 which is coupled to the same sensing circuit 300 as the bit line connected to the memory cell to be read. For the description below, it is assumed that bit line 121a is coupled to node A1 and is the bit line connected to the memory cell 100 to be read, while bit line 121b is coupled to node A2 and is the other bit line (also known as the reference bit line). However, one skilled in the art would recognize that the roles of the bit lines may be changed depending on which memory cell is being read. The equalization circuit 310 also includes two output nodes A3 and A4, which are respectively coupled to input nodes A5 and A6 of the reference setting circuit 320. Additionally, the equalization circuit 310 accepts, from a control circuit 350 the EQ control signal at node C1. In addition, the equalization circuit 310 accepts the equalization voltage Veq voltage at node P1.
The function of the equalization circuit 310 is to equalize the voltages of the bit lines 121a, 121b respectively coupled to nodes A1, A2 to the Veq voltage level. The sense process performed by the sensing circuit 300 begins with the operation of the equalization circuit 310, in which the EQ control signal, which is typically asserted low, is temporarily asserted high. While the EQ control signal is asserted high, bit lines 121a and 121b are coupled to each other and also coupled to the Veq voltage. After a short time, both bit lines are charged to the Veq voltage. The EQ control signal is then returned to a low state, thereby decoupling bit lines 121a and 121b from each other and from the Veq voltage. The parasitic capacitance on the bit lines 121a, 121b holds the bit line voltage at the Veq level.
The reference setting circuit 320 is used to change the voltage on one of the two bit lines 121a, 121b from the Veq voltage to a predetermined voltage Vref. The control circuit 350 temporarily asserts high one of control signals REFE (at node C2) and REFO (at node C3) to select the bit line having the memory cell 100 to be read as the bit line for changing the voltage. The reference setting circuit 320 also accepts power at the DVC2 (at node P2) and Vref (at node P3) voltages.
The isolation circuit 330, is a switch for controllably coupling or decoupling the sense amplifier 340 from the reference setting circuit 320, and the from the bit lines coupled to nodes A1 and A2. The isolation circuit 320 accepts the SA_ISO control signal, which is normally asserted low to isolate the sense amplifier 340 from the reference setting circuit 320.
After the reference setting circuit 320 has set bit line 121b to the predetermined voltage Vref, and while the SA_ISO control signal is asserted low, the word line 122 associated with the memory cell 100 to be read is asserted high for a predetermined time and then asserted low. During the predetermined time, the access transistor 101 of the memory cell 100 is set to a conductive state, thereby causing the bit line 121a associated with the memory cell 100 being read to discharge through the cell plate 110. As a result, the bit line 121a associated with the memory cell 100 being read is now at a lower voltage. Depending upon the state of the memory cell 100, the lower voltage is either at a first lower voltage which is higher in voltage than the Vref voltage, or a second lower voltage which is lower in voltage than the Vref voltage.
The SA_ISO control signal is then asserted high to couple the sense amplifier 340 to both bit lines 121a, 121b. The sense amplifier 340 is also respectively coupled to a Vcc power supply voltage and a ground potential voltage at nodes P4 and P5. Bit line 121a has either a slightly higher or lower voltage than bit line 121b, based on the state of memory cell 100. The sense amplifier 340 magnifies the voltage difference by pulling the lower voltage bit line to ground and pulling the higher voltage bit line to a higher voltage. When the sense amplifier has completed this operation, a comparator (not illustrated) associated with the sense amplifier 340 can be used to output a high or low logical state corresponding to the state of the memory cell 100 at node O1.
As described above, the sensing circuit 300 is coupled to a variety of voltages supplied by a power supply. These include the Veq, DVC2, Vref, and Vcc voltages. The requirement to provide each additional voltage from a power supply 360 makes the power supply more complicated. Accordingly, there is a need and desire to reduce the number of power supply taps required by the sensing circuit of a resistive memory, thereby reducing power consumption.